Robert Schilling

Robert Schilling

Silicon Engineer

Meta

Silicon engineer at Meta working on platform security for custom silicon.

Previously at Rivos Inc. (acquired by Meta), where I led the development of Darjeeling, the SoC-integrated variant of OpenTitan, an open-source silicon root of trust — from design through tapeout, silicon bringup, and full provisioning.

Ph.D. from Graz University of Technology — hardware extensions and compiler support for fault-attack countermeasures on RISC-V processors. Active bug bounty researcher with 42 CVEs discovered in GitLab. Passionate about automation and building reusable, scalable hardware-software co-designs that extend beyond security.

Interests
  • Platform Security
  • Silicon Root of Trust
  • Fault Attacks and Countermeasures
  • Hardware-Software Codesign
  • Post-Quantum Cryptography
  • Bug Bounty / Vulnerability Research
Education
  • PhD in Computer Science, 2023

    Graz University of Technology

  • MSc in Information and Computer Engineering, 2016

    Graz University of Technology

  • BSc in Information and Computer Engineering, 2013

    Graz University of Technology

Experience

 
 
 
 
 
Silicon Engineer
February 2026 – Present Cambridge, UK
  • Platform security for Meta’s custom silicon
  • Working on Caliptra, an open-source hardware root of trust for data center SoCs
 
 
 
 
 
Security Architect
Rivos Inc. (acquired by Meta)
April 2023 – February 2026 Graz, Austria
  • Led development of Darjeeling, the SoC-integrated variant of OpenTitan (open-source silicon root of trust)
  • FIPS 140-3 readiness for OpenTitan’s security subsystem
  • Tapeout, full silicon bringup, and provisioning
  • Upstreamed Darjeeling to the open-source OpenTitan project
 
 
 
 
 
University Assistant
April 2019 – April 2023 Graz, Austria
  • Research related to secure code execution in the presence of physical attacks
  • Teaching: Computer Organization and Networks, Digital System Design
 
 
 
 
 
Research Assistant
April 2016 – March 2019 Graz, Austria
Research related to secure code execution in the presence of physical attacks
 
 
 
 
 
Software Developer
May 2010 – January 2015 Gratkorn, Austria
Lead development for automated measurement systems used for NFC-IC verification

Industry Talks

Migrating a Silicon Root of Trust to Post-Quantum Crypto
OpenTitan Integrated: A RISC-V Open-Source Silicon Root-of-Trust for Large SoCs

Security Research

Active participant in the GitLab Bug Bounty Program with 42 CVEs discovered across access control, information disclosure, XSS, and authentication bypass categories.

View full CVE list →

Publications

FAULTLESS: Flexible and Transparent Fault Protection for Superscalar RISC-V Processors
Hardware Extensions and Compiler Support for Protection Against Fault Attacks
Multi-Tag: A Hardware-Software Co-Design for Memory Safety based on Multi-Granular Memory Tagging
SCFI: State Machine Control-Flow Hardening Against Fault Attacks
SFP: Providing System Call Flow Protection against Software and Fault Attacks
FIPAC: Thwarting Fault- and Software-Induced Control-Flow Attacks with ARM Pointer Authentication
Protecting Indirect Branches Against Fault Attacks Using ARM Pointer Authentication
SecWalk: Protecting Page Table Walks Against Fault Attacks
CrypTag: Thwarting Physical and Logical Memory Vulnerabilities using Cryptographically Colored Memory
HECTOR-V: A Heterogeneous CPU Architecture for a Secure RISC-V
ConTExT: A Generic Approach for Mitigating Spectre
Protecting RISC-V Processors against Physical Attacks
Securing Conditional Branches in the Presence of Fault Attacks
Small Faults Grow Up - Verification of Error Masking Robustness in Arithmetically Encoded Programs
Pointing in the Right Direction - Securing Memory Accesses in a Faulty World
High Speed ASIC Implementations of Leakage-Resilient Cryptography
Leakage Bounds for Gaussian Side Channels
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics
Transparent Memory Encryption and Authentication
Multi-Core Data Analytics SoC with a Flexible 1.76 Gbit/s AES-XTS Cryptographic Accelerator in 65 nm CMOS
A Low-Area ASIC Implementation of AEGIS128—A fast Authenticated Encryption Algorithm